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Ambarella featured in EDN.com: “Ambarella’s Unique View on the Future of Digital Cameras Leads to a Unique View on SoC Architecture”

January 05, 2009

Monday, January 5, 2009

Image-processing SoC vendor Ambarella has always had a unique view of the end markets they serve. Today, for example, executive vice president Didier Le Gall sees an inevitable merging of the digital still camera and camcorder markets. “There is a new demographic out there,” Le Gall says. “They are growing up with YouTube. Hand-held video clips are their idea of a snapshot. For them—and they will be an important portion of the market—the future of the digital still camera is to become a camcorder.” Le Gall went on to speculate that the future of both may be to become part of the feature set of a handset.

This view of the world seems consistent with the way young consumers use their handsets today—not to take snapshots with mediocre quality, but to record video clips with mediocre quality. Unskilled, 8mm-like video has developed a cult status, in much the same way that certain plastic, medium-format film cameras with really awful optical quality have developed a cult following around the world. The point isn’t the quality, or even the subject. The point is the egalitarian informality of the recording and viewing experiences.

Remarkably enough, given this attitude toward image quality, the SoCs to support video recording are moving as rapidly as possible toward real high-definition (HD) video capability. That means frames in the neighborhood of 10 Mpixels at 60 frames per second interlaced. “The higher refresh rate smoothes out some of the camera-motion issues when you pan with a hand-held device,” Le Gall says. “Going to 60 fps progressive-scan would be better, but there is still no infrastructure out there to support video streams at that bit rate, and 60 i looks a lot better on the display than 30 p.”

Such data rates create a huge problem for the SoC design team, according to Le Gall. But it’s not the problem you might think of first. Processing speed is not the issue, really. Ambarella’s macroarchitecture, a well-kept secret, appears to have changed little beyond their initial concept of a cluster of SIMD-based accelerators surrounding an ARM supervisory processor. Today, the latest A5 processor is capable of performing its considerable processing repertoire on video streams up to 5 Mpixels at 60 fps, according to Le Gall. It is specified to handle 10 Mpixel still images at 9 frames per second, or, as mentioned, HD video at 60i. The problem is that there is no place to put the data at that rate, except into the DRAM directly interfaced to the SoC.

The real problem, then, is bandwidth—and especially memory bandwidth. All of those processor blocks within the chip have to be designed with enough local memory so that the aggregate worst-case bus demand doesn’t overload the SoC’s internal bus. And the whole system has to be designed so that it uses its DRAM port as efficiently as possible.

This is a matter of correct function: if an overloaded bus or interface stalls, there could be visual artifacts. But it is also a matter of another overriding concern for hand-held devices: power. A demonstration of how important power is now is that along with the A5, Ambarella is quietly rolling out a reduced-power version of their earlier A2 SoC. Because data movement is a major source of energy consumption in video SoCs, particularly at the interfaces, efficient data movement is a power issue.

Le Gall says that achieving efficiency in data movement begins with the algorithms being architected to move data as little as possible, and as locally as possible. Then the problem becomes one of efficient on-chip memory instanciation in support of the algorithms. And only then does the responsibility of energy efficiency devolve to the circuitry and process.

For years organizations such as IMEC have been preaching that data movement is the key to energy efficiency. But there are still surprisingly few tools, especially at the system level, to assist architects and chip designers in analyzing this major issue, or for that matter, to help model the system to verify the adequacy of interconnect and interface bandwidth. This can be good news for design teams with strong algorithm-development experience, as they may have more leverage over energy than teams whose strength is in chip design only. And in these times, such skills can be a wonderful job-security measure for designers who have them.

http://www.edn.com/blog/1690000169/post/1400038740.html

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